1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a power line control circuit of a semiconductor device.
2. Discussion of Related Art
In general, internal circuits included in the semiconductor device employ internal voltages, which are generated based on externally supplied and relatively high voltages, as operating power thereof. For this end, the semiconductor device includes power lines for transmitting the internal circuits with the internal voltages, respectively. The arrangement of the power lines and the widths of the power lines may be varied depending on the operating environments of the semiconductor device, the size of the semiconductor device and/or the like.
In recent years, with the developments of semiconductor manufacture technology, the power lines has become minute as the semiconductor device is miniaturized and is more highly integrated. However, as the width of the power line is narrowed, a resistance value of the power line is increased. As a result, the internal voltages transferred through the power lines are lowered due to voltage drop incurred by the resistance of the power lines.
If the internal voltages are lowered as described above, however, the internal circuits may malfunction. Therefore, the width of the power lines must be properly controlled depending on the operating characteristics of the internal circuits.
In other words, it is preferred that the power lines are formed such that the internal circuits of the semiconductor device operate in an optimal way. Consequently, proper arrangement of the power lines and the width of the power lines may play an important role in improving the operating performance of the semiconductor device.
FIG. 1 is a view schematically illustrating power lines and internal circuits of a semiconductor device in the related art.
Referring to FIG. 1, internal circuits 21 to 26 are connected to power lines 11 to 13, respectively. The power lines 11 to 13 are formed to have widths D1, D2, and 3D such that the internal circuits 21 to 26 operate in an optimal state.
To decide the widths of the power lines 11 to 13, which meet the optimal operating condition of the internal circuits 21 to 26, a power line formation process employing a mask must be repeatedly performed. This is because it does not know whether the internal circuits 21 to 26 can operate as an optimal state when each of the power lines 11 to 13 has what width. Therefore, a manufacturer can decide an optimal width of each of the power lines 11 to 13 by increasing or decreasing the widths of the power lines 11 to 13 through a test process.
This will be described in more detail. In the test process, the manufacturer confirms the operating state of each of the internal circuits 21 to 26 while changing the width of each of the power lines 11 to 13 using a pattern process employing a mask. As a result, the widths of the power lines 11 to 13, in which the internal circuits 21 to 26 can operation optimally, can be decided.
In the test process, however, the pattern processes of the power lines 11 to 13 must be repeatedly carried out in order to decide the widths of the power lines 11 to 13. Accordingly, a problem arises because the manufacturing cost and the manufacturing time of the power lines 11 to 13 are increased.